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* Remove old test codeMiquel Sabaté Solà2024-12-055-360/+0
| | | | | | | | | | | There is some code that I had there after messing with some of the topics on Uros' blog (https://popovicu.com/), but that became irrelevant after working on some other projects (e.g. fbos) or on other examples. This commit also brings about a major overhaul on the structure of the project. Hopefully it's now at a more ready state. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Add a strcmp exampleMiquel Sabaté Solà2024-12-052-0/+38
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Do not force a CROSS_COMPILE valueMiquel Sabaté Solà2024-12-051-4/+3
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* arch/riscv/usr: Add t0 in the clobber listMiquel Sabaté Solà2024-12-051-1/+1
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Fix Makefile by allowing cross compilationMiquel Sabaté Solà2024-12-051-5/+5
| | | | | | | Since it was entirely developed on a real RISC-V board, I did not notice issues with cross compilation. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an improved example on early boot stageMiquel Sabaté Solà2024-12-051-7/+7
| | | | | | This also implied a renaming arch/riscv/bios -> arch/riscv/machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Add a note on Zawrs extensionMiquel Sabaté Solà2024-12-051-2/+13
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an example on RISC-V atomic addsMiquel Sabaté Solà2024-12-052-1/+43
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Restructure the whole thingMiquel Sabaté Solà2024-12-055-0/+270
It will be something more than just messing around with RISC-V stuff. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>