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authorMiquel Sabaté Solà <mikisabate@gmail.com>2024-08-28 22:25:56 +0200
committerMiquel Sabaté Solà <mikisabate@gmail.com>2024-12-05 16:02:49 +0100
commitab03d3be21f229be8c28dba292d5da237a929a73 (patch)
tree8bc53e3031f644532fec255bb392a90cd4ad59fb /arch/riscv/bios/hello.s
parent1a36e6211674f1a39c7cc0ddff705357a4add65a (diff)
downloadfarga-ab03d3be21f229be8c28dba292d5da237a929a73.tar.gz
farga-ab03d3be21f229be8c28dba292d5da237a929a73.zip
Restructure the whole thing
It will be something more than just messing around with RISC-V stuff. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
Diffstat (limited to 'arch/riscv/bios/hello.s')
-rw-r--r--arch/riscv/bios/hello.s23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/riscv/bios/hello.s b/arch/riscv/bios/hello.s
new file mode 100644
index 0000000..f3aa20a
--- /dev/null
+++ b/arch/riscv/bios/hello.s
@@ -0,0 +1,23 @@
+# From: https://github.com/qemu/qemu/blob/23fa74974d8c96bc95cbecc0d4e2d90f984939f6/hw/riscv/virt.c#L82.
+.set QEMU_UART0_ADDRESS, 0x10000000
+
+.global _start
+.section .text.bios
+
+_start: li a0, 0x68
+ li a1, QEMU_UART0_ADDRESS
+ sb a0, (a1) # 'h'
+
+ li a0, 0x65
+ sb a0, (a1) # 'e'
+
+ li a0, 0x6C
+ sb a0, (a1) # 'l'
+
+ li a0, 0x6C
+ sb a0, (a1) # 'l'
+
+ li a0, 0x6F
+ sb a0, (a1) # 'o'
+
+loop: j loop