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##
# This is a very minimalistic linker configuration for UNROM chips. This
# configuration assumes the standard UNROM configuration, with two regions
# defined that split $8000-$FFFF, where the first half is swappable. For the
# bank switching there are 7 banks, which coupled with the fixed region it sums
# up 128KB of total PRG-ROM.
#
# NOTE: it assumes that only assembly is being used, and thus a lot of magic
# required for C programs is missing.
# NOTE: it is following the example of games such as Castlevania or Megaman.
# Thus, there is no CHR segment because it's all done through RAM.
MEMORY {
# iNES header.
HEADER: start = $0, size = $10, fill = yes;
# Program RAM. Available if a battery-backed RAM was requested.
WRAM: file = "" start = $6000, size = $2000, define = yes;
# Swappable ROM addresses. Note the filled values. This is done so it's also
# clear by inspecting the memory which bank we are on. This can come in
# handy when inspecting things with an hex editor.
PRG0: start = $8000, size = $4000, fill = yes, fillval = $f8, define = yes;
PRG1: start = $8000, size = $4000, fill = yes, fillval = $f9, define = yes;
PRG2: start = $8000, size = $4000, fill = yes, fillval = $fa, define = yes;
PRG3: start = $8000, size = $4000, fill = yes, fillval = $fb, define = yes;
PRG4: start = $8000, size = $4000, fill = yes, fillval = $fc, define = yes;
PRG5: start = $8000, size = $4000, fill = yes, fillval = $fd, define = yes;
PRG6: start = $8000, size = $4000, fill = yes, fillval = $fe, define = yes;
# Fixed ROM address.
PRG: start = $C000, size = $3FFA, fill = yes, fillval = $ff, define = yes;
ROMV: start = $FFFA, size = $0006, fill = yes;
}
SEGMENTS {
# iNES header.
HEADER: load = HEADER, type = ro;
# This is the fixed bank, that spans $C000-$FFFF. Make sure to put the reset
# code and basic stuff that you don't want ever to be gone here. This will
# include stuff like the reset code, bank switching utilities, etc.
FIXED: load = PRG, type = ro, define = yes;
VECTORS: load = ROMV, type = ro, define = yes;
##
# Swappable banks.
BANK0: load = PRG0, type = ro;
BANK1: load = PRG1, type = ro;
BANK2: load = PRG2, type = ro;
BANK3: load = PRG3, type = ro;
BANK4: load = PRG4, type = ro;
BANK5: load = PRG5, type = ro;
BANK6: load = PRG6, type = ro;
}
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