1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
MEMORY {
# iNES header.
HEADER: start = $0, size = $10, fill = yes;
# Banked PRG ROM.
PRG0: start = $8000, size = $4000, fill = yes, fillval = $f8, define = yes;
PRG1: start = $C000, size = $3FFA, fill = yes, fillval = $f9, define = yes;
# Hardware Vectors.
ROMV: start = $FFFA, size = $0006, fill = yes;
# Banked CHR banks.
ROM2_0: start = $0000, size = $2000, fill = yes, fillval = $11;
ROM2_1: start = $2000, size = $2000, fill = yes, fillval = $22;
}
SEGMENTS {
HEADER: load = HEADER, type = ro;
BANK0: load = PRG0, type = ro;
BANK1: load = PRG1, type = ro;
VECTORS: load = ROMV, type = ro;
CHR0: load = ROM2_0, type = ro;
CHR1: load = ROM2_1, type = ro;
}
|