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* linux: Add a program to test the hwprobe syscallMiquel Sabaté Solà2024-12-053-0/+355
| | | | | | | RISC-V on Linux has a hwprobe system call which allows you to discover what is supported by the running kernel. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Add a strcmp exampleMiquel Sabaté Solà2024-12-052-0/+38
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Do not force a CROSS_COMPILE valueMiquel Sabaté Solà2024-12-051-4/+3
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* kernel/dtm: ensure that the cpu node is releasedMiquel Sabaté Solà2024-12-051-6/+5
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* kernel/dtm: Add an example on the kernel DT APIMiquel Sabaté Solà2024-12-055-0/+170
| | | | | | | This comes in the form of a simple kernel module which iterates over CPUs and prints the contents of some device tree nodes. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* machine: Use the proper ABI definitionMiquel Sabaté Solà2024-12-053-2/+2
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* arch/riscv/usr: Add t0 in the clobber listMiquel Sabaté Solà2024-12-051-1/+1
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Fix Makefile by allowing cross compilationMiquel Sabaté Solà2024-12-051-5/+5
| | | | | | | Since it was entirely developed on a real RISC-V board, I did not notice issues with cross compilation. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an improved example on early boot stageMiquel Sabaté Solà2024-12-0510-65/+296
| | | | | | This also implied a renaming arch/riscv/bios -> arch/riscv/machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Add a note on Zawrs extensionMiquel Sabaté Solà2024-12-051-2/+13
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an example on RISC-V atomic addsMiquel Sabaté Solà2024-12-052-1/+43
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Restructure the whole thingMiquel Sabaté Solà2024-12-0523-1/+124
| | | | | | It will be something more than just messing around with RISC-V stuff. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Add an example on floating instructionsMiquel Sabaté Solà2024-12-054-7/+68
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Fix typo on 'palindrome'Miquel Sabaté Solà2024-12-052-19/+19
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Add some examples on RISC-V assemblyMiquel Sabaté Solà2024-12-055-0/+213
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Initial commitMiquel Sabaté Solà2024-12-0515-0/+198
Mainly with the code I took from @popovicu's blog. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>