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* btrfs: add this directory into the main README.mdMiquel Sabaté Solà2026-02-242-1/+2
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* vdso: fix typo and styling issuesMiquel Sabaté Solà2026-02-241-40/+35
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* btrfs: add examples on the shutdown experimental featureMiquel Sabaté Solà2026-02-245-1/+299
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* kernel/vdso: Add an example on vDSOMiquel Sabaté Solà2025-09-224-0/+247
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* lang/c: Add an example on flexible array checksMiquel Sabaté Solà2025-09-134-0/+127
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* riscv: user: Force LINUX_HEADERS on hwprobeMiquel Sabaté Solà2025-04-225-12/+49
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* riscv: user: Statically build everythingMiquel Sabaté Solà2025-04-222-2/+2
| | | | | | | | This way these binaries can be executed from virtually anywhere, like my minimalistic busybox setup I have for QEMU which doesn't even have the `ld-` files required to run a C program. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* riscv: user: Update constants for Zicntr and ZihpmMiquel Sabaté Solà2025-04-221-13/+4
| | | | | | | | | | | A patch from me has finally been merged into the Linux Kernel, and the values for these constants have been increased by one due to the inclusion of another patch. Moreover, the Zicsr and Zifencei extensions have not been exported yet, but they might not make sense to include them after all. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* supervisor: Add an example on the HSM extensionMiquel Sabaté Solà2024-12-0510-3/+614
| | | | | | | | | | | | The HSM extension from SBI v2.0 allows a supervisor to manage the state of harts on the system. Moreover, it also guarantees that only one hart makes it into the booting stages of the supervisor, and it's up to the supervisor to wake up the rest through the HSM extension. I have added an example which showcases this extension in different ways, and it finally shuts down the machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Remove old test codeMiquel Sabaté Solà2024-12-0521-145/+693
| | | | | | | | | | | There is some code that I had there after messing with some of the topics on Uros' blog (https://popovicu.com/), but that became irrelevant after working on some other projects (e.g. fbos) or on other examples. This commit also brings about a major overhaul on the structure of the project. Hopefully it's now at a more ready state. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* linux: Add a program to test the hwprobe syscallMiquel Sabaté Solà2024-12-053-0/+355
| | | | | | | RISC-V on Linux has a hwprobe system call which allows you to discover what is supported by the running kernel. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Add a strcmp exampleMiquel Sabaté Solà2024-12-052-0/+38
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* usr: Do not force a CROSS_COMPILE valueMiquel Sabaté Solà2024-12-051-4/+3
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* kernel/dtm: ensure that the cpu node is releasedMiquel Sabaté Solà2024-12-051-6/+5
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* kernel/dtm: Add an example on the kernel DT APIMiquel Sabaté Solà2024-12-055-0/+170
| | | | | | | This comes in the form of a simple kernel module which iterates over CPUs and prints the contents of some device tree nodes. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* machine: Use the proper ABI definitionMiquel Sabaté Solà2024-12-053-2/+2
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* arch/riscv/usr: Add t0 in the clobber listMiquel Sabaté Solà2024-12-051-1/+1
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Fix Makefile by allowing cross compilationMiquel Sabaté Solà2024-12-051-5/+5
| | | | | | | Since it was entirely developed on a real RISC-V board, I did not notice issues with cross compilation. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an improved example on early boot stageMiquel Sabaté Solà2024-12-0510-65/+296
| | | | | | This also implied a renaming arch/riscv/bios -> arch/riscv/machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Add a note on Zawrs extensionMiquel Sabaté Solà2024-12-051-2/+13
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an example on RISC-V atomic addsMiquel Sabaté Solà2024-12-052-1/+43
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Restructure the whole thingMiquel Sabaté Solà2024-12-0523-1/+124
| | | | | | It will be something more than just messing around with RISC-V stuff. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Add an example on floating instructionsMiquel Sabaté Solà2024-12-054-7/+68
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Fix typo on 'palindrome'Miquel Sabaté Solà2024-12-052-19/+19
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Add some examples on RISC-V assemblyMiquel Sabaté Solà2024-12-055-0/+213
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Initial commitMiquel Sabaté Solà2024-12-0515-0/+198
Mainly with the code I took from @popovicu's blog. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>