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* btrfs: add examples on the shutdown experimental featureMiquel Sabaté Solà2026-02-241-1/+5
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* kernel/vdso: Add an example on vDSOMiquel Sabaté Solà2025-09-221-0/+1
| | | | Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com>
* lang/c: Add an example on flexible array checksMiquel Sabaté Solà2025-09-131-0/+3
| | | | Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* supervisor: Add an example on the HSM extensionMiquel Sabaté Solà2024-12-051-2/+3
| | | | | | | | | | | | The HSM extension from SBI v2.0 allows a supervisor to manage the state of harts on the system. Moreover, it also guarantees that only one hart makes it into the booting stages of the supervisor, and it's up to the supervisor to wake up the rest through the HSM extension. I have added an example which showcases this extension in different ways, and it finally shuts down the machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Remove old test codeMiquel Sabaté Solà2024-12-051-3/+2
| | | | | | | | | | | There is some code that I had there after messing with some of the topics on Uros' blog (https://popovicu.com/), but that became irrelevant after working on some other projects (e.g. fbos) or on other examples. This commit also brings about a major overhaul on the structure of the project. Hopefully it's now at a more ready state. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* linux: Add a program to test the hwprobe syscallMiquel Sabaté Solà2024-12-051-0/+1
| | | | | | | RISC-V on Linux has a hwprobe system call which allows you to discover what is supported by the running kernel. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* kernel/dtm: Add an example on the kernel DT APIMiquel Sabaté Solà2024-12-051-0/+9
| | | | | | | This comes in the form of a simple kernel module which iterates over CPUs and prints the contents of some device tree nodes. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Provide an improved example on early boot stageMiquel Sabaté Solà2024-12-051-1/+1
| | | | | | This also implied a renaming arch/riscv/bios -> arch/riscv/machine. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* Restructure the whole thingMiquel Sabaté Solà2024-12-051-1/+7
| | | | | | It will be something more than just messing around with RISC-V stuff. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
* basics: Add some examples on RISC-V assemblyMiquel Sabaté Solà2024-12-051-0/+2
Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>